NVIDIA Nemotron 3 Ultra leads in chip design accuracy

NVIDIA has demonstrated that its Nemotron 3 Ultra model, when paired with the ACE-RTL agent, achieves state-of-the-art performance in automated chip design. On the Comprehensive Verilog Design Problems (CVDP) benchmark, this combination achieved a 97.1% average pass rate across nine Register Transfer Level (RTL) task categories. This setup outperformed rival models, with Kimi K2.6 reaching a 95.2% pass rate and GLM 5.2 achieving 92.1%. In specific debugging and fixing tasks, the ACE-RTL agent boosted Nemotron 3 Ultra's standalone pass rate from 65.7% to a perfect 100%, while GLM 5.2 rose from 44.0% to 94.3% and Kimi K2.6 improved from 68.6% to 97.1%.

Beyond accuracy, Nemotron 3 Ultra proved highly resource-efficient. It consumed an average of 6,629 tokens per iteration, which is roughly 28% fewer than GLM 5.2's 9,156 tokens and 71% fewer than Kimi K2.6's 22,579 tokens. This efficiency stems from its hybrid Mamba-Attention Mixture-of-Experts architecture, which features 550 billion total parameters and 55 billion active parameters. Pretrained on 20 trillion text tokens with a 1 million-token context length, the model delivers up to five times higher throughput and 30% lower costs than comparable open models.

For hardware engineers, these advancements make iterative, agentic RTL workflows highly practical. Instead of manually writing and debugging Verilog code, practitioners can deploy the model to automatically generate code, analyze simulation failures, and apply fixes. The reduced token usage directly translates to lower compute costs and faster design iterations. To support these workflows, the open model is already being integrated into major electronic design automation ecosystems. These include Cadence's ChipStack, InnoStack, ViraStack, and AuraStack AI Super Agents; Siemens' Questa One Agentic Toolkit and Fuse EDA AI Agent; and Synopsys' AgentEngineer with its Openshell Sandbox.