OpenAI and Synopsys Partner to Build GPT-Synopsys AI

OpenAI and electronic design automation software provider Synopsys have entered into a multi-year strategic partnership to develop a specialized artificial intelligence model named GPT-Synopsys. Under the agreement, OpenAI is licensing Synopsys' proprietary electronic design automation tools to train the new system. The resulting model will run on OpenAI's cloud infrastructure, with both companies planning to co-market the product and share the generated revenues.

The primary objective of GPT-Synopsys is to create an AI system capable of reasoning through the intricate processes of chip design and verification. Rather than acting as a simple assistant, the model is being built to directly operate Synopsys' software. Human engineers will be able to delegate high-level design objectives to the AI, focusing their efforts on reviewing and approving the generated outputs. To address intellectual property concerns, the companies have committed to encrypting all customer data and ensuring it is not used to train future iterations of the model. Early testing with select semiconductor customers is already underway.

According to Synopsys CEO Sassine Ghazi, integrating AI into the workflow could drastically accelerate the traditional chip design pipeline. OpenAI co-founder Greg Brockman noted that the collaboration represents a dual pathway toward producing both superior hardware and more advanced AI systems. This partnership aligns with OpenAI's broader hardware ambitions, which include a separate collaboration with Broadcom to develop custom silicon. That effort recently yielded the Jalapeno chip, a specialized processor designed to run AI workloads.

For semiconductor engineers and chip designers, this development signals a shift toward highly automated workflows. By offloading routine design and verification tasks to GPT-Synopsys, practitioners can transition from manual layout creation to high-level system architecture and oversight. This transition could significantly reduce time-to-market for new microprocessors, allowing smaller design teams to compete in a rapidly evolving hardware landscape.